Low Voltage Controller for Touch Screens AD7879
FEATURES
4-wire touch screen interface 1.6 V to 3.6 V operation Median and averaging filter to reduce noise Automatic conversion sequencer and timer User-programmable conversion parameters Auxiliary analog input/battery monitor (0.5 V to 5 V) 1 optional GPIO Interrupt outputs (INT, PENIRQ) Touch-pressure measurement Wake-up on touch function Shutdown mode: 6 A maximum 12-ball, 1.6 mm x 2 mm WLCSP 16-lead, 4 mm x 4 mm LFCSP
FUNCTIONAL BLOCK DIAGRAM
VCC/REF
X- Y- X+ Y+ X+ X- REF- Y+
6-TO-1 MUX
REF-
REF+
Y- GND TEMPERATURE SENSOR
12-BIT SAR ADC
FILTERING
RESULT REGISTERS
PENIRQ/INT/DAV
07667-001
AUX/VBAT/GPIO
AD7879/ AD7879-1
CONTROL REGISTERS
APPLICATIONS
Personal digital assistants Smart hand-held devices Touch screen monitors Point-of-sale terminals Medical devices Cell phones
SERIAL PORT TO RESULT REGISTERS CS/ DIN/ DOUT/ SCL ADD0 ADD1 SDA
SEQUENCER AND TIMER
Figure 1.
GENERAL DESCRIPTION
The AD7879 is a 12-bit successive approximation analog-todigital converter (ADC) with a synchronous serial interface and low on-resistance switches for driving 4-wire resistive touch screens. The AD7879 works with a very low power supply (a single 1.6 V to 3.6 V) and features throughput rates of 105 kSPS. The device includes a shutdown mode that reduces its current consumption to less than 6 A. To reduce the effects of noise from LCDs and other sources, the AD7879 contains a preprocessing block. The preprocessing function consists of a median and an averaging filter. The combination of these two techniques provides a more robust solution, discarding the spurious noise in the signal and keeping only the data of interest. The size of both filters is programmable. Other user-programmable conversion controls include variable acquisition time and first conversion delay; up to 16 averages can be taken per conversion. The AD7879 can run in either slave or standalone mode, using an automatic conversion sequencer and timer. The AD7879 has a programmable pin that can operate as an auxiliary input to the ADC, as a battery monitor, or as a GPIO. There is also a programmable interrupt output that can operate in three modes: as a general-purpose interrupt to signal when new data is available INT, as an interrupt to indicate when limits are exceeded, or as a pen-down interrupt when the screen is touched (PENIRQ). The AD7879 offers temperature measurement and touch-pressure measurement. The AD7879 is available in a 12-ball, 1.6 mm x 2 mm WLCSP and in a 16-lead, 4 mm x 4 mm LFCSP. The part also has either an SPI (AD7879) or I2C (AD7879-1) interface.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD7879 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 SPI Timing Specifications (AD7879) ......................................... 4 I C Timing Specifications (AD7879-1) ..................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 11 Theory of Operation ...................................................................... 12 Touch Screen Principles ............................................................ 12 Measuring Touch Screen Inputs ............................................... 13 Touch-Pressure Measurement .................................................. 14 Temperature Measurement ....................................................... 14 Median and Averaging Filters ....................................................... 16 AUX/VBAT/GPIO Pin ................................................................... 17
2
Auxiliary Input ........................................................................... 17 Battery Input ............................................................................... 17 Limit Comparison ...................................................................... 17 GPIO ............................................................................................ 17 Register Map ................................................................................... 19 Detailed Register Descriptions ..................................................... 20 Control Registers ............................................................................ 24 Control Register 1 ...................................................................... 24 Control Register 2 ...................................................................... 26 Control Register 3 ...................................................................... 27 Interrupts ..................................................................................... 28 Synchronizing the AD7879 to the Host CPU......................... 29 Serial Interface ................................................................................ 30 SPI Interface ................................................................................ 30 I2C-Compatible Interface .......................................................... 32 Grounding and Layout .................................................................. 35 Chip Scale Packages ................................................................... 35 WLCSP Assembly Considerations ........................................... 35 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 36
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD7879 SPECIFICATIONS
VCC = 1.6 V to 3.6 V, TA = -40C to +85C, unless otherwise noted. Table 1.
Parameter DC ACCURACY Resolution No Missing Codes Integral Nonlinearity (INL)1 Differential Nonlinearity (DNL)1 Negative DNL Positive DNL Offset Error2 Gain Error2 Noise3 Power Supply Rejection3 Internal Clock Frequency SWITCH DRIVERS On Resistance1 Y+, X+ Y-, X- ANALOG INPUTS Input Voltage Ranges DC Leakage Current Input Capacitance Accuracy TEMPERATURE MEASUREMENT Temperature Range Resolution Accuracy2 BATTERY MONITOR Input Voltage Range Input Impedance3 Accuracy LOGIC INPUTS (DIN, SCL, CS, SDA, GPIO) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS (DOUT, GPIO, SCL, SDA, INT) Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2 CONVERSION RATE3 Conversion Time Throughput Rate POWER REQUIREMENTS VCC (Specified Performance) ICC Converting Mode Static Shutdown Mode
1 2 3
Min 12 11
Typ
Max
Unit Bits Bits LSB LSB LSB LSB LSB V rms dB MHz
Test Conditions/Comments
12 3 -0.99 +2 6 4
LSB size = 390 V LSB size = 390 V
2 70 60 2
6 5 0 0.1 30 0.3 -40 0.3 2 0 16 2 0.7 VCC 0.3 VCC 0.01 10 VCC - 0.2 0.4 0.1 5 9.5 105 1.6 2.6 480 406 0.5 3.6 650 5 5 +85 VCC
V A pF % C C C V k % V V A pF V V A pF s kSPS V A A A Digital inputs = 0 V or VCC ADC on, PM = 10 ADC and temperature sensor are off; the reference and oscillator are on; PM = 01, 11 PM = 00 Including 2 s of acquisition time
Calibrated at 25C
Uncalibrated accuracy
VIN = 0 V or VCC
6
See the Terminology section. Guaranteed by characterization, not production tested. Sample tested at 25C to ensure compliance.
Rev. 0 | Page 3 of 36
AD7879
SPI TIMING SPECIFICATIONS (AD7879)
TA = -40C to +85C; VCC = 1.6 V to 3.6 V, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V. Table 2.
Parameter 1 fSCLK t1 t2 t3 t4 t5 t6 t7 t8
1
Limit at TMIN, TMAX 5 5 20 20 15 15 20 16 15
Unit MHz max ns min ns min ns min ns min ns min ns max ns max ns min
Description CS falling edge to first SCL falling edge SCL high pulse width SCL low pulse width DIN setup time DIN hold time DOUT access time after SCL falling edge CS rising edge to DOUT high impedance SCL rising edge to CS high
Guaranteed by design, not production tested.
CS
t1
t2
1 2
t3
3 15 16 1 2 15
t8
16
SCL
t4 t5
DIN MSB LSB
t6
DOUT MSB LSB
t7
07667-002
Figure 2. Detailed SPI Timing Diagram
Rev. 0 | Page 4 of 36
AD7879
I2C TIMING SPECIFICATIONS (AD7879-1)
TA = -40C to +85C; VCC = 1.6 V to 3.6 V, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals are timed from a voltage level of 1.4 V. Table 3.
Parameter 1 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 tR tF
1
Limit 400 0.6 1.3 0.6 100 300 0.6 0.6 1.3 300 300
Unit kHz max s min s min s min ns min ns min s min s min s min ns max ns max
Description Start condition hold time, tHD; STA Clock low period, tLOW Clock high period, tHIGH Data setup time, tSU; DAT Data hold time, tHD; DAT Stop condition setup time, tSU; STO Start condition setup time, tSU; STA Bus free time between stop and start conditions, tBUF Clock/data rise time Clock/data fall time
Guaranteed by design, not production tested.
t2
SCL
tR
tF
t1
t1 t5
SDA
t3 t4
t7
t6
STOP START
START
STOP
Figure 3. Detailed I2C Timing Diagram
Rev. 0 | Page 5 of 36
07667-003
t8
AD7879 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise specified. Table 4.
Parameter VCC to GND Analog Input Voltage to GND AUX/VBAT to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 ESD Rating (X+, Y+, X-, Y-) Air Discharge Human Body Model Contact Human Body Model ESD Rating (All Other Pins) Human Body Discharge Field Induced Charge Device Model Machine Model Operating Temperature Range Storage Temperature Range Junction Temperature WLCSP (4-Layer Board) Power Dissipation JA Thermal Impedance LFCSP (4-Layer Board) Power Dissipation JA Thermal Impedance IR Reflow Peak Temperature Lead Temperature (Soldering 10 sec)
1
Rating -0.3 V to +3.6 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 5 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V 10 mA 15 kV 10 kV 4 kV 1 kV 0.2 kV -40C to +85C -65C to +150C 150C 866 mW 75C/W 2.138 W 30.4C/W 260C (0.5C) 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
200A IOL
TO OUTPUT PIN
1.4V CL 50pF 200A IOH
07667-004
Figure 4. Circuit Used for Digital Timing
ESD CAUTION
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. 0 | Page 6 of 36
AD7879 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1 INDICATOR 1 2
AUX/ VBAT/ GPIO VCC/REF
3
X+
BALL A1 INDICATOR 1 2
AUX/ VBAT/ GPIO VCC/REF
3
X+
A
PENIRQ/ INT/DAV CS Y+
A
PENIRQ/ INT/DAV ADD0 Y+
B
DOUT DIN X-
B
SDA ADD1 X-
C
SCL GND Y-
C
SCL GND Y-
D
07667-005
D TOP VIEW (BALL SIDE DOWN) Not to Scale TOP VIEW (BALL SIDE DOWN) Not to Scale
07667-006
Figure 5. AD7879 WLCSP Pin Configuration
13 AUX/VBAT/GPIO
Figure 7. AD7879-1 WLCSP Pin Configuration
13 AUX/VBAT/GPIO
16 X+ 15 VCC/REF
16 X+ 15 VCC/REF
Y+ 1 NC 2 NC 3 X- 4
PIN 1 INDICATOR
12 PENIRQ/INT/DAV 11 NC 10 NC 9 DOUT
Y+ 1 NC 2 NC 3 X- 4
PIN 1 INDICATOR
14 ADD0
14 CS
12 PENIRQ/INT/DAV 11 NC 10 NC 9 SDA
AD7879
TOP VIEW (Not to Scale)
AD7879-1
TOP VIEW (Not to Scale)
SCL 8
GND 7
NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
07667-007
ADD1 6
GND 7
SCL 8
Y- 5
DIN 6
Y- 5
Figure 6. AD7879 LFCSP Pin Configuration
Figure 8. AD7879-1 LFCSP Pin Configuration
Table 5. Pin Function Descriptions
WLCSP 1A 1B 1C 1D 2A 2B 2C 2D 3A 3B 3C 3D N/A N/A Pin No. LFCSP 13 12 9 8 15 14 6 7 16 1 4 5 2, 3, 10, 11 17 Mnemonic AUX/VBAT/GPIO PENIRQ/INT/DAV DOUT SDA SCL VCC/REF CS ADD0 DIN ADD1 GND X+ Y+ X- Y- NC EP Description Pin functionality is programmable to be either an auxiliary input to the ADC, as a battery measurement input to the ADC, or as a general-purpose digital input/output. Interrupt Output. This pin asserts either when the screen is touched, when new data is available in the registers, or when a measurement exceeds the preprogrammed limits. Active low, internal pull-up resistor of 50 k. SPI Serial Data Output on the AD7879. Serial Data Input and Output on the AD7879-1. Serial Interface Clock Input. Power Supply Input. It is also the ADC reference. Chip Select for the Serial Interface on the AD7879. Active low. Address Bit 0 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1. SPI Serial Data Input to the AD7879. Address Bit 1 for the AD7879-1. This pin can be tied high or low to determine an address for the AD7879-1. Ground. Ground reference point for all circuitry on the AD7879. All analog input signals and any external reference signal should be referred to this voltage. Touch Screen Input Channel. Touch Screen Input Channel. Touch Screen Input Channel. Touch Screen Input Channel. No Connect. Exposed Pad.
Rev. 0 | Page 7 of 36
07667-008
AD7879 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VCC = 2.6 V, fSAMPLE = 125 kHz, fDCLK = 16 x fSAMPLE = 2 MHz, unless otherwise noted.
475 470
GAIN ERROR VARIATION (LSB)
1.0 0.8 0.6 0.4 0.2 0 3.6V -0.2 -0.4 1.6V -0.6 -0.8
07667-009
465 460
CURRENT (A)
455 450 445 440 435 430 425 -40 -25 -10 10 25 40 TEMPERATURE (C) 55 70 85
2.6V
-40
-25
-10
10 25 40 TEMPERATURE (C)
55
70
85
Figure 9. Supply Current vs. Temperature
Figure 12. Change in ADC Gain vs. Temperature
700
1.0 0.8 0.6
600 500
OFFSET VARIATION (LSB)
0.4 0.2
CURRENT (A)
1.6V 2.6V
400
0 -0.2 3.6V -0.4 -0.6
300
200 100
-0.8
07667-010
1.6
1.8
2.0
2.2
2.4
2.6 2.8 VCC (V)
3.0
3.2
3.4
3.6
-40
-25
-10
10 25 40 TEMPERATURE (C)
55
70
85
Figure 10. Supply Current vs. VCC
Figure 13. Change in ADC Offset vs. Temperature
4.0 3.5 3.0
CURRENT (A)
2.0 1.5 1.0 0.5 INL (LSB) 0
2.5 2.0 1.5 1.0 0.5
07667-012
-0.5 -1.0 -1.5
07667-014
0 -40 -25 -10 10 25 50 TEMPERATURE (C) 75 100
-2.0 0 512 1024 1536 2048 CODE 2560 3072 3584 4096
Figure 11. Full Power-Down IDD vs. Temperature
Figure 14. ADC INL Plot
Rev. 0 | Page 8 of 36
07667-013
0
-1.0
07667-011
-1.0
AD7879
1.0 0.8 0.6 0.4
DNL (LSB)
6.0
5.5
5.0
RON ()
0.2 0 -0.2 -0.4 -0.6 -0.8
07667-015
4.5
4.0 X+ TO VCC X- TO GND Y+ TO VCC Y- TO GND -40 -25 -10 10 25 40 TEMPERATURE (C) 55 70 85
07667-017 07667-018
3.5
-1.0 1 501 1001 1501 2001 2501 CODE 3001 3501 4001
3.0
Figure 15. ADC DNL Plot
Figure 17 Switch On Resistance vs. Temperature (X+, Y+: VCC to Pin; X-, Y-: Pin to GND)
7
2370 2369
6 2368
ADC CODE (Decimal)
07667-016
5
2367 2366 2365 2364 2363 2362 2361
RON ()
4
3 X+ TO VCC Y+ TO VCC X- TO GND Y- TO GND
2 1
0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 VCC (V) 3.0 3.2 3.4 3.6
2360 -40 -25 -15 -5 5 15 25 35 45 TEMPERATURE (C) 55 65 75 85
Figure 16. Switch On Resistance vs. VCC (X+, Y+: VCC to Pin; X-, Y-: Pin to GND)
Figure 18. ADC Code vs. Temperature (Fixed Analog Input)
Rev. 0 | Page 9 of 36
AD7879
1400
1200 1000
MEAN: -1.98893 SD: 0.475534 250
TEMPERATURE (Code)
800
NUMBER OF UNITS
07667-019
200
150
600
100
400 200
50
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V)
-4
-3
-2 ERROR (%)
-1
0
Figure 19. Temperature Code vs. VCC for 25C
Figure 21. Typical Uncalibrated Accuracy for Battery Channel (25C)
0 -20
INPUT TONE AMPLITUDE (dB)
SNR = 61.58dB THD = 72.34dB
-40 -60 -80 -100 -120 -140 -160
0 1603 3206 4809 6412 8015 9618 11221 12824 14427 16030 17633 19236 20839 22442 24045 25648 27251 28854 30457 32060 33663 35266 36869
FREQUENCY (Hz)
Figure 20. Typical FFT Plot for the Auxiliary Channels at 25 kHz Sampling Rate and 1 kHz Input Frequency
07667-020
Rev. 0 | Page 10 of 36
07667-021
0
0
AD7879 TERMINOLOGY
Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at 1 LSB below the first code transition and full scale at 1 LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error Offset error is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal (AGND + 1 LSB). Gain Error Gain error is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (VREF - 1 LSB) after the offset error has been adjusted out. On Resistance On resistance is a measure of the ohmic resistance between the drain and the source of the switch drivers.
Rev. 0 | Page 11 of 36
AD7879 THEORY OF OPERATION
The AD7879 is a complete, 12-bit data acquisition system for digitizing positional inputs from a 4-wire resistive touch screen. To support this function, data acquisition on the AD7879 is highly programmable so as to ensure accurate and noise free results from the touch screen. The core of the AD7879 is a high speed, low power, 12-bit analog-to-digital converter (ADC) with input multiplexer, on-chip track-and-hold, and on-chip clock. Conversion results are stored in on-chip results registers. The results from the auxiliary input or the battery input can be compared with high and low limits stored in limit registers to generate an outof-limit INT. The AD7879 also contains low resistance analog switches to switch the X and Y excitation voltages to the touch screen and the on-chip temperature sensor. The high speed SPI serial bus provides control of the devices, as well as communication with the device. The AD7879-1 is available with an I2C interface. Operating from a single supply from 1.6 V to 3.6 V, the AD7879 offers a throughput rate of 105 kHz. The device is available in a 1.6 mm x 2 mm 12-ball wafer level chip scale package (WLCSP) and in a 4 mm x 4 mm 16-lead lead frame chip scale package. The AD7879 has an on-chip sequencer that schedules a sequence of preprogrammed conversions. The conversion sequence starts automatically when the screen is touched, or at preset intervals, using the on-board timer. To ensure that the AD7879 works well with different touch screens, the user can select the acquisition time. There is also a programmable delay to ensure that the voltage on the touch screen settles before a measurement is taken. To help reduce noise in the system, the ADC takes up to 16 conversion results from each channel, and writes the average of the results to the register. To further improve the performance of the AD7879, the median filter can also be used if there is noise present in the system.
CONDUCTIVE ELECTRODE ON TOP SIDE LCD SCREEN CONDUCTIVE ELECTRODE ON BOTTOM SIDE Y+ PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON BOTTOM SIDE
X- Y-
X+
Figure 22. Basic Construction of a Touch Screen
The Y layer has conductive electrodes running along the top and bottom edges, allowing the application of an excitation voltage down the Y layer from top to bottom. Provided that the layers are of uniform resistivity, the voltage at any point between the two electrodes is proportional to the horizontal position for the X layer and the vertical position for the Y layer. When the screen is touched, the two layers make contact. If only the X layer is excited, the voltage at the point of contact, and therefore the horizontal position, can be sensed at one of the Y layer electrodes. Similarly, if only the Y layer is excited, the voltage, and therefore the vertical position, can be sensed at one of the X layer electrodes. By switching alternately between X and Y excitation and measuring the voltages, the X and Y coordinates of the contact point can be found. In addition to measuring the X and Y coordinates, it is also possible to estimate the touch pressure by measuring the contact resistance between the X and Y layers. The AD7879 is designed to facilitate this measurement.
TOUCH SCREEN PRINCIPLES
A 4-wire touch screen consists of two flexible, transparent, resistive-coated layers that are normally separated by a small air gap. The X layer has conductive electrodes running down the left and right edges, allowing the application of an excitation voltage across the X layer from left to right.
Rev. 0 | Page 12 of 36
07667-022
PLASTIC FILM WITH TRANSPARENT, RESISTIVE COATING ON TOP SIDE
AD7879
Figure 23 shows an equivalent circuit of the analog input structure of the AD7879, showing the touch screen switches, the main analog multiplexer, the ADC, and the dual 3-to-1 multiplexer that selects the reference source for the ADC.
VCC
The voltage seen at the input to the ADC in Figure 24 is
VIN = VCC x
RY - RYTOTAL
(1)
X+ X- Y+ Y- INPUT MUX AUX/VBAT/GPIO REF- TEMPERATURE SENSOR IN+ REF+ 12-BIT SUCCESSIVE APPROXIMATION ADC WITH TRACK-AND-HOLD
07667-023
The advantage of the single-ended method is that the touch screen excitation voltage is switched off once the signal is acquired. Because a screen can draw over 1 mA, this is a significant consideration for a battery-powered system. The disadvantage of the single-ended method is that voltage drops across the switches can introduce errors. Touch screens can have a total end-to-end resistance ranging from 200 to 900 . By taking the lowest screen resistance of 200 and a typical switch resistance of 14 , the user can reduce the apparent excitation voltage to 200/228 x 100 = 87% of its actual value. In addition, the voltage drop across the low-side switch adds to the ADC input voltage. This introduces an offset into the input voltage; thus, it can never reach zero.
X- Y- GND X+ Y+ VCC DUAL 3-TO-1 MUX
Ratiometric Method
The ratiometric method illustrated in Figure 25 shows the negative input of the ADC reference tied to Y- and the positive input connected to Y+. Thus, the screen excitation voltage provides the reference for the ADC. The input of the ADC is connected to X+ to determine the Y position.
VCC
Figure 23. Analog Input Structure
The AD7879 can be set up to automatically convert either specific input channels or a sequence of channels. The results of the ADC conversions are stored in the results registers. When measuring the ancillary analog inputs (AUX, TEMP, or VBAT), the ADC uses a VCC reference and the measurement is referred to GND.
MEASURING TOUCH SCREEN INPUTS
When measuring the touch screen inputs, it is possible to measure using VCC as a reference, or to use the touch screen excitation voltage as the reference and to perform a ratiometric, differential measurement. The differential method is the default method and is selected by clearing the SER/DFR bit (Bit 9 in Control Register 2) to 0. The single-ended method is selected by setting this bit to 1.
Y+
X+
INPUT (VIA MUX)
REF+ ADC
TOUCH SCREEN Y-
REF-
GND
Figure 25. Ratiometric Conversion of Touch Screen Inputs
Single-Ended Method
Figure 24 illustrates the single-ended method for the Y position. For the X position, the excitation voltage is applied to X+ and X- and the voltage is measured at Y+.
VCC
Y+
VREF REF+ ADC
For greater accuracy, the ratiometric method has two significant advantages. One is that the reference to the ADC is provided from the actual voltage across the screen; therefore, any voltage dropped across the switches has no effect. The other advantage is that because the measurement is ratiometric, it does not matter if the voltage across the screen varies in the long term. However, it must not change after the signal has been acquired. The disadvantage of the ratiometric method is that the screen must be powered up at all times because it provides the reference voltage for the ADC.
X+
INPUT (VIA MUX)
TOUCH SCREEN
REF- Y-
07667-024
GND
Figure 24. Single-Ended Conversion of Touch Screen Inputs
Rev. 0 | Page 13 of 36
07667-025
AD7879
TOUCH-PRESSURE MEASUREMENT
The pressure applied to the touch screen by a pen or finger can also be measured with the AD7879, using some simple calculations. The contact resistance between the X and Y plates is measured providing a good indication of the size of the depressed area and, therefore, the applied pressure. The area of the spot that is touched is proportional to the size of the object touching it. The size of this resistance (RTOUCH) can be calculated using two different methods.
Second Method
The second method requires the user to know the resistance of the X-plate and Y-plate tablets. Three touch screen conversions are required: a measurement of the X position (XPOSITION), the Y position (YPOSITION), and the Z1 position. The following equation also calculates the RTOUCH: RTOUCH = RXPLATE x (XPOSITION/4096) x [(4096/Z1) - 1] - RYPLATE x [1 - (YPOSITION/4096)] (3)
First Method
The first method requires the user to know the total resistance of the X-plate tablet (RX). Three touch screen conversions are required: measurement of the X position, XPOSITION (Y+ input); measurement of the Y- input with the excitation voltage applied to Y+ and X- (Z1 measurement); and measurement of the X+ input with the excitation voltage applied to Y+ and X- (Z2 measurement). These three measurements are illustrated in Figure 26. The AD7879 has two special ADC channel settings that configure the X and Y switches for Z1 and Z2 measurement and store the results in the Z1 and Z2 results registers. The Z1 measurement is ADC Channel 101b, and the result is stored in register with Read Address 0x0A. The Z2 measurement is ADC Channel 100b, and the result is stored in register with Read Address 0x0B. The touch resistance can then be calculated using the following equation: RTOUCH = (RXPLATE) x (XPOSITION /4096) x [(Z2/Z1) - 1]
MEASURE X POSITION X+ TOUCH RESISTANCE Y+
TEMPERATURE MEASUREMENT
A temperature measurement option called the single conversion method is available on the AD7879. The conversion method requires only a single measurement on ADC Channel 001b. The results are stored in the results registers with Address 0x0D (TEMP). The AD7879 does not provide an explicit output of the temperature reading; the system must perform some external calculations. This method is based on an on-chip diode measurement. The acquisition time is fixed at 16 ms for temperature measurement.
Conversion Method
The conversion method makes use of the fact that the temperature coefficient of a silicon diode is approximately -2.1 mV/C. However, this small change is superimposed on the diode forward voltage, which can have a wide tolerance. Therefore, it is necessary to calibrate by measuring the diode voltage at a known temperature to provide a baseline from which the change in forward voltage with temperature can be measured. This method provides a resolution of approximately 0.3C and a predicted accuracy of 2C. The temperature limit comparison is performed on the result in the TEMP results register, which is the measurement of the diode forward voltage. The values programmed into the high and low limits should be referenced to the calibrated diode forward voltage to make accurate limit comparisons.
(2)
X-
Y- MEASURE Z1 POSITION
Y+ TOUCH RESISTANCE
X+
Y-
X-
Y+ TOUCH RESISTANCE
X+
Y-
X- MEASURE Z2 POSITION
07667-026
Figure 26. Three Measurements Required for Touch Pressure
Rev. 0 | Page 14 of 36
AD7879
Temperature Calculations
If an explicit temperature reading in degrees Celsius is required, calculate for the single measurement method by 1. Calculate the scale factor of the ADC in degrees per LSB Degrees per LSB = ADC LSB size/-2.1 mV = (VCC/4096)/-2.1 mV 2. 3. 4. Save the ADC output (DCAL) at the calibration temperature, TCAL. Take the ADC reading, DAMB, at the temperature to be measured, TAMB. Calculate the difference in degrees between TCAL and TAMB by T = (DAMB - DCAL) x degrees per LSB 5. Add T to TCAL.
Example
Using VCC = 2.5 V as reference, Degrees per LSB = (2.5/4096)/-2.1 x 10-3 = -0.291 The ADC output is 983 decimal at 25C, equivalent to a diode forward voltage of 0.6 V. The ADC output at TAMB is 880. T = (880 - 983) x -0.291 = 30C TAMB = 25 + 30 = 55C
Rev. 0 | Page 15 of 36
AD7879 MEDIAN AND AVERAGING FILTERS
As explained in the Touch Screen Principles section, touch screens are composed of two resistive layers, normally placed over an LCD screen. Because these layers are in close proximity to the LCD screen, noise can be coupled from the screen onto these resistive layers, causing errors in the touch screen positional measurements. The AD7879 contains a filtering block to process the data and discard the spurious noise before sending the information to the host. The goal of this block is not just the suppression of noise; the on-chip filtering also remarkably reduces the host processing loading. The processing function consists of two filters that are applied to the converted results: the median filter and the averaging filter. The median filter suppresses the isolated out-of-range noise and sets the number of measurements to be taken. These measurements are arranged in a temporary array, where the first value is the smallest measurement and the last value is the largest measurement. Bit 6 and Bit 5 in Control Register 2 (M1, M0) set the window of the median filter, and therefore, the number of measurements taken. Table 6. Median Filter Size
M1 0 0 1 1 M0 0 1 0 1 Function Median filter does not operate 4 measurements 8 measurements 16 measurements
When both filter values are 00, only one measurement is transferred to the register map. The number chosen with the M1 and M0 settings must be equal to or larger than the number chosen with the A1 and A0 settings. If both settings select the same number, the median filter is switched off. Table 8. Median Averaging Filters (MAVF) Settings
M=A MA Function Median filter does not operate; output is the average of A converted results Not possible because the median filter size is always bigger than the averaging window size Output is the average of the middle A values from the array of M measurements
Example
M1, M0 = 11, A1, A0 = 10; in this example the median filter has a window size of 16. This means that 16 measurements are taken and arranged in descending order in a temporary array. The averaging window size in this case is 8. The output is an average of the middle 8 values of the 16 measurements taken with the median filter.
12-BIT SAR ADC CONVERTED RESULTS 6 2 13 4 16 5 15 10 9 3 11 8 1 12 14 7
MEDIAN FILTER 16 MEASUREMENTS ARRANGED 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AVERAGING FILTER AVERAGE OF MIDDLE 8 VALUES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
The averaging filter size determines the number of values to average. Bit 8 and Bit 7 in Control Register 2 (A1, A0) allow the average of 2, 4, 8, or 16 samples. Only the final averaged result is written into the results register. Table 7. Averaging filter Size
A1 0 0 1 1 A0 0 1 0 1 Function Average of 2 middle samples Average of 4 middle samples Average of 8 middle samples Average of 16 samples
M = 16
A=8
Figure 27. Median and Averaging Filter Example
Rev. 0 | Page 16 of 36
07667-027
AD7879 AUX/VBAT/GPIO PIN
Pin 1A (AUX/VBAT/GPIO) on the AD7879 can be programmed as either an auxiliary input to the ADC, as a battery monitoring input, or as a general-purpose digital input/output. To select the auxiliary measurement, set the ADC channel address to 011. To select a battery measurement, set the ADC channel address to 010. To select the GPIO, set Bit 13 in Control Register 2 (Address 0x02) to 1.
LIMIT COMPARISON
The AUX measurement and the battery measurement can be compared with high and low limits stored on-chip. An out-of-limit result generates an alarm output at the INT pin (PENIRQ/INT/DAV) provided the INT function is enabled. The high limit for both channels is stored in Register 0x04, while the low limit is stored in Register 0x05. After a measurement from either AUX or VBAT is taken, it is compared with the high and low limits. The out-of-limit comparison sets a status bit in Control Register 3. There are separate status bits for both the high and low limits to indicate which limit was exceeded. The interrupt sources can be masked by clearing the corresponding enable bit in this register.
AUXILIARY INPUT
The AD7879 has an auxiliary analog input, AUX. When selected, the signal on the AUX pin (AUX/VBAT/GPIO) is connected directly to the ADC input. This channel has a full-scale input range from 0 V to VCC. The ADC channel addresses for AUX is 011, and the result is stored in Register 0x0C.
BATTERY INPUT
The AD7879 can monitor battery voltages from 0.5 V to 5 V when the BAT measurement is selected. Figure 28 shows a block diagram of a battery voltage monitored through the VBAT pin. The voltage to the VCC pin (VCC/REF) of the AD7879 is maintained at the desired supply voltage via the dc-to-dc regulator while the input to the regulator is monitored. This voltage on VBAT is divided down by 4 internally, so that a 5 V battery voltage is presented to the ADC as 1.25 V. To conserve power, the divider circuit is on only during the sampling of a voltage on VBAT. Note that the possible maximum input is 5 V. The VBAT input is ADC Channel 010, and the result is stored in Register 0x0C.
DC-TO-DC CONVERTER BATTERY 0.5V TO 5V VBAT 12k SW 0.125V TO 1.25V ADC VCC
GPIO
The AD7879 has one general-purpose logic input/output pin, GPIO (AUX/VBAT/GPIO). To enable the GPIO, set Bit 13 in Control Register 2 to 1. If this bit it 0, then the AUX/VBAT function is active on the pin. The other GPIO configuration bits have no effect, if the GPIO is not enabled. The GPIO data bit is located in Bit 12 of the Control Register 2.
Direction (Bit 11, Control Register2, Address 0x02)
Bit 11 sets the direction of the GPIO pin (AUX/VBAT/GPIO). When GPIO DIR = 0, the pin is an output. Setting or clearing bits in the GPIO data bit (Register 0x02[12]) outputs a value on the GPIO pin. When GPIO DIR = 1, the pin is an input. An input value on the GPIO pin sets or clears the GPIO data bit (Register 0x02[12]). GPIO data register bits are read-only when GPIO DIR = 1.
Polarity (Bit 10, Control Register 2, Address 0x02)
When GPIO POL = 0, the GPIO pin is active low. When GPIO POL = 1, the GPIO pin is active high. How this bit affects the GPIO operation also depends on the GPIO DIR bit. If GPIO POL = 1 and GPIO DIR = 1, a 1 at the input pin sets the corresponding GPIO data register bit to 1. A 0 at the input pin clears the corresponding GPIO data bit to 0. If GPIO POL = 1 and GPIO DIR = 0, a 1 in the GPIO data register bit puts a 1 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 0 on the GPIO output pin. If GPIO POL = 0 and GPIO DIR = 1, a 1 at the input pin sets the corresponding GPIO data bit to 0. A 0 at the input pin clears the corresponding GPIO data bit to 1. If GPIO POL = 0 and GPIO DIR = 0, a 1 in the GPIO data register bit puts a 0 on the corresponding GPIO output pin. A 0 in the GPIO data register bit puts a 1 on the GPIO output pin.
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4k
Figure 28. Block Diagram of Battery Measurement Circuit
The maximum battery voltage that the AD7879 can measure changes when a different reference voltage is used. The maximum voltage that is measurable is VCC x 4 because this voltage gives a full-scale output from the ADC. The battery voltage can be calculated using the following formula: VBAT (V) = [(Register Value) x VCC x 4]/4095
Rev. 0 | Page 17 of 36
AD7879
GPIO Interrupt Enable (Bit 12, Control Register 3, Address 0x03)
The GPIO pin can operate as an interrupt source to trigger the INT output. This is controlled by Bit 12 in Control Register 3. If the GPIO ALERT interrupt enable = 1, the GPIO can trigger INT. If this bit = 0, the GPIO cannot trigger INT. INT is asserted if the GPIO data register bit is set when the GPIO is configured as an input, provided that INT is enabled. INT is triggered only when the GPIO is configured as an input, that is, when GPIO DIR = 1. INT is clear only when the GPIO signal or the GPIO enable changes.
Rev. 0 | Page 18 of 36
AD7879 REGISTER MAP
Table 9. Register Table
Address 1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E
1
Name Unused Control Register 1 Control Register 2 Control Register 3 AUX/VBAT high limit AUX/VBAT low limit TEMP high limit TEMP low limit X+ Y+ X+ (Z1) Y- (Z2) AUX/VBAT TEMP Revision and device ID
Description Unused PENIRQ enable, channel selection for manual selection, ADC mode, acquisition time, and conversion timer ADC power management, GPIO control, pen interrupt, averaging, median filter, software reset, and FCD Status of high/low limit comparisons for TEMP, AUX/VBAT and enable bits to allow them to become interrupts; channel selection for slave/master mode AUX/VBAT high limit for comparison AUX/VBAT low limit for comparison TEMP high limit for comparison TEMP low limit for comparison X+ measurement for Y position Y+ measurement for X position X+ measurement for touch pressure calculation (Z1) Y- measurement for touch pressure calculation (Z2) AUX/VBAT measurement Temperature conversion Measurement Revision and device ID
Default Value 0x0000 0x0000 0x4040 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0379 (AD7879-1) 0x037A (AD7879)
Type R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R
Do not write to addresses outside the register map.
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AD7879 DETAILED REGISTER DESCRIPTIONS
All addresses and default values are expressed in hexadecimal. Table 10. Control Register 1
Address 0x01 Name Disable PENIRQ Data Bit 15 Description Pen interrupt enable. 0 = PENIRQ pin is enabled. 1 = PENIRQ is disabled and INT enabled. CHNL ADD[2:0] 14:12 ADC Channel address for manual conversion (mode 01). 111 = X+ input (Y position). 110 = Y+ input (X position). 101 = X+ (Z1) input for touch-pressure calculation. 100 = Y- (Z2) input (used for touch-pressure measurement). 011 = AUX input 1 . 010 = VBAT input1. 001 = temperature measurement. 000 = not applicable. ADC mode. 00 = no conversion. 01 = single conversion 2 . 10 = conversion sequence (slave mode)2. 11 = conversion sequence (master mode). ADC acquisition time. 00 = 4 clock periods (2 s). 01 = 8 clock periods (4 s). 10 = 16 clock periods (8 s). 11 = 32 clock periods (16 s). Note that the acquisition time does not apply to the temperature sensor channels; the temperature channel has a constant settling time of 16 s. Conversion interval timer. Starts at 550 s and continues to 9.440 ms in steps of 35 s. Note that in slave mode, the conversion interval timer starts to count as soon as the conversion sequence is finished; in master mode, it starts to count again only if the screen remains touched. If the screen is released, the timer stops counting and, on the next screen touch, a conversion starts immediately. Default Value 0x0000
ADC MODE[1:0]
11:10
ACQ[1:0]
9:8
TMR[7:0]
7:0
1 2
If GPIO is enabled, AUX and VBAT are both ignored. If AUX and VBAT are both selected, and GPIO is disabled, AUX is ignored, and VBAT is measured. Note that these settings clear to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (0x01) Bits 7:0 = 0x00h at the end of the conversion sequence.
Rev. 0 | Page 20 of 36
AD7879
Table 11. Control Register 2
Address 0x02 Name PM[1:0] Data Bit 15:14 Description ADC power management. 00 = full shutdown, the ADC, oscillator, BIAS, and temperature sensor are all powered down. 01 = analog blocks to be powered down depend on the ADC mode. If ADC mode is master mode; the ADC, oscillator, BIAS, and temperature sensor are powered down and must wake up when the user touches the screen. If ADC mode is slave mode, the ADC and temperature sensor are powered down while not being used. They wake up automatically when required. The oscillator and BIAS are powered up because they are needed to measure time. This also applies to the single conversion mode. 10 = ADC, BIAS, the oscillator is powered up continuously, irrespective of ADC mode. 11 = as 01. GPIO enable. 0 = AUX/VBAT channel active. 1 = GPIO enabled on AUX/VBAT/GPIO. GPIO data bit. GPIO direction. 0 = output. 1 = input. GPIO polarity. 0 = the GPIO pin is active low. 1 = the GPIO pin is active high. SER/DFR. Selects normal (single-ended) or conversion. 0 = ratiometric (differential). 1 = normal (single-ended). ADC averaging. 00 = 2 middle values averaged (1 measurement when median filter does not operate). 01 = 4 middle values averaged. 10 = 8 middle values averaged. 11 = 16 values averaged. Median filter size. 00 = median filter does not operate. 01 = 4 measurements. 10 = 8 measurements. 11 = 16 measurements. Software reset; digital part is reset when this bit is set. ADC first conversion delay 1 . Starts at 128 s and goes all the way to 4.096 ms in steps of 128 s. Default Value 0x4040
GPIO EN
13
GPIO DAT GPIO DIR
12 11
GPIO POL
10
SER/DFR
9
A[1:0]
8:7
M[1:0]
6:5
SW/RST FCD[3:0]
4 3:0
1
This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the ADC to power up.
Rev. 0 | Page 21 of 36
AD7879
Table 12. Control Register 3
Address 0x03 Name TEMP MASK Data Bit 15 Description TEMP mask bit 0 = temperature measurement is allowed to cause interrupt 1 = temperature measurement is not allowed to cause interrupt AUX/VBAT mask bit 0 = AUX/VBAT measurement is allowed to cause interrupt 1 = AUX/VBAT measurement is not allowed to cause interrupt DAV/INT mode select 0 = enable DAV mode 1 = enable INT mode GPIO ALERT 12 Note that this bit overrides any mask bits associated with individual channels GPIO interrupt enable 0 = GPIO can cause an alert on the INT output 1 = mask GPIO from causing an alert on the INT output AUX/VBAT LOW AUX/VBAT HIGH TEMP LOW TEMP HIGH X+ Y+ Z1 Z2 AUX VBAT TEMP Not used
1
Default Value 0x0000
AUX/VBAT MASK INT MODE
14
13
11 10 9 8 7 6 5 4 3 2 1 0
1 = AUX/VBAT below low limit 1 = AUX/VBAT above high limit 1 = TEMP below low limit 1 = TEMP above high limit 1 = include measurement of Y position (X+ input) 1 = include measurement of X position (Y+ input) 1 = include Z1 touch pressure measurement (X+ input) 1 = include measurement of Z2 touch pressure measurement (Y- input) 1 = include measurement of AUX channel 1 1 = include measurement of battery monitor (VBAT)1 1 = include temperature measurement Unused
If GPIO is enabled, AUX and VBAT are both ignored. If AUX and VBAT are both selected, and GPIO is disabled, AUX is ignored, and VBAT is measured.
Table 13. Limit Registers
Address 0x04 0x05 0x06 0x07 Data Bit 15:0 15:0 15:0 15:0 Description User-programmable AUX/VBAT high limit register User-programmable AUX/VBAT low limit register User-programmable TEMP high limit register User-programmable TEMP low limit register Default Value 0x0000 0x0000 0x0000 0x0000
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AD7879
Table 14. Measurement Result Registers
Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D Data Bit 15:0 15:0 15:0 15:0 15:0 15:0 Description Measured X+ input with Y excitation (Y position) Measured Y+ input with X excitation (X position) Measured X+ input with X- and Y+ excitation (touch-pressure calculation Z1) Measured Y- input with X- and Y+ excitation (touch-pressure calculation Z2) AUX/VBAT voltage measurement Temperature conversion measurement Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
Table 15. Revision/Device ID Register
Address 0x0E Data Bit 15:12 11:8 7:0 Description Unused Revision and device ID bits Device ID Default Value 0x0379 (AD7879-1) 0x037A (AD7879)
Rev. 0 | Page 23 of 36
AD7879 CONTROL REGISTERS
15 0
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DIS CHNL CHNL CHNL ADC ADC ACQ1 ACQ0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 PENIRQ ADD2 ADD1 ADD0 MODE1 MODE0
Figure 29. Control Register 1
CONTROL REGISTER 1
Control Register 1 (Address 0x01) contains the ADC channel address and the ADC mode bits. It sets the acquisition time and the timer. It also contains a bit to disable the pen interrupt. Control Register 1 should always be the last register programmed prior to starting conversions. Its power-on default value is 0x0000. To change any parameter after conversion has begun, the part should first be put into Mode 00. Make the changes; then reprogram Control Register 1, ensuring that it is always the last register programmed before conversions begin.
ADC Mode (Control Register 1, Bits[11:10])
The mode bits select the operating mode of the ADC. The AD7879 has three operating modes. These are selected by writing to the mode bits in Control Register 1. If the mode bits are 00, no conversion is performed. Table 18. Control Register 1 Mode Selection
ADC MODE1 0 0 1 1 ADC MODE0 0 1 0 1 Function Do not convert (default) Single-channel conversion; the AD7879 is in slave mode Sequence 0; the AD7879 is in slave mode Sequence 1; the AD7879 is in master mode
Timer (Control Register 1, Bits[7:0])
The TMR bits in Control Register 1 enable the ADC to repeatedly perform a conversion or to perform a conversion sequence only once or at intervals of 35 s from 550 s up to 9.440 ms. In slave mode, the timer starts as soon as the conversion sequence is finished. In master mode, the timer starts at the end of a conversion sequence only if the screen remains touched. If the touch is released at any stage, then the timer stops. The next time the screen is touched, a conversion sequence immediately begins. Table 16. Control Register 1 Timer Selection
TMR 00000000 00000001 00000010 00000011 ... 11111101 11111110 11111111 Function Convert one time only (default) Every 550 s Every 585 s Every 620 s ... Every 9.370 ms Every 9.405 ms Every 9.440 ms
If the mode bits are 01, a single conversion is performed on the channel selected by writing to the channel bits of Control Register 1 (Bit 12 to Bit 14). At the end of the conversion, if the TMR bits in Control Register 1 are set to 00000000, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a value other than 00000000 causes the conversion to be repeated. The AD7879 can also be programmed to automatically convert a sequence of selected channels. The two modes for this type of conversion are slave mode and master mode. For slave mode operation, the channels to be digitized are selected by setting the corresponding bits in Control Register 3. Conversion is initiated by writing 10b to the mode bits of Control Register 1. The ADC then digitizes the selected channels and stores the results in the corresponding results registers. At the end of the conversion, if the TMR bits in Control Register 1 are set to 00000000, the mode bits revert to 00 and the ADC returns to no convert mode until a new conversion is initiated by the host. Setting the TMR bits to a code other than 00000000 causes the conversion sequence to be repeated. For master mode operation, the channels to be digitized are written to the Control Register 3. Master mode is then selected by writing 11 to the mode bits in Control Register 1. In this mode, the wake-up on touch feature is active; therefore, conversion does not immediately begin. The AD7879 waits until the screen is touched before beginning the sequence of conversions. The ADC then digitizes the selected channels; and the results are written to the result registers. The AD7879 waits for the screen to be touched again, or for a timer event if the screen remains touched, before beginning another sequence of conversions.
Acquisition Time (Control Register 1, Bits[9:8])
The ACQ bits in Control Register 1 allow the selection of acquisition times for the ADC of 2 s (default), 4 s, 8 s, or 16 s. The user can program the ADC with an acquisition time suitable for the type of signal being sampled. For example, signals with large RC time constants can require longer acquisition times. Table 17. Acquisition Time Selection
ACQ1 0 0 1 1 ACQ0 0 1 0 1 Function 4 clock periods (2 s) 8 clock periods (4 s) 16 clock periods (8 s) 32 clock periods (16 s)
Rev. 0 | Page 24 of 36
AD7879
ADC Channel (Control Register 1 Bits[14:12])
The ADC channel is selected by Bits[14:12] of Control Register 1 (CHNL ADD2 to CHNL ADD0). A complete list of channel addresses is given in Table 19. For Mode 0 (single-channel) conversion, the channel is selected by writing the appropriate CHNL ADD2 to CHNL ADD0 code to Control Register 1. For sequential channel conversion, channels to be converted are selected by setting bits corresponding to the channel number in the Control Register 3 for slave and master mode sequencing. For both single-channel and sequential conversion, a normal conversion (single-ended) is selected by clearing the SER/DFR bit in Control Register 2 (Bit 9). Ratiometric (differential) conversion is selected by setting the SER/DFR bit.
PENIRQ Enable (Control Register 1, Bit 15)
The AD7879 has a dual function output that performs as PENIRQ or INT depending on the pen interrupt enable bit (Bit 15 of Control Register 1). When this bit is set to 0, the pin is working as a pen interrupt and it goes low whenever the screen is touched. When the pen interrupt enable bit is set to 1, the pin interrupt request is disabled and the pin functions as INT.
Table 19. Codes for Selecting Input Channel and Normal or Ratiometric Conversion
Channel 0 1 2 3 4 5 6 7 8 9 12 13 14 15 SER/DFR 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CHNL ADD[2:0] 111 110 101 100 011 010 001 000 111 110 101 100 011 010 001 000 Analog Input X+ (Y position) Y+ (X position) X+ (Z1 touch pressure) Y- (Z2 touch pressure) AUX VBAT TEMP X+ (Y position) Y+ (X position) X+ (Z1 touch pressure) Y- (Z2 touch pressure) AUX VBAT TEMP X Switches Y Switches Off On On Off X+ off, X- on Y+ on, Y- off X+ off, X- on Y+ on, Y- off Off Off Off Off Off Off Invalid address Off On On Off Off Off Off Off Off Off Off Off Off Off Invalid address +REF Y+ X+ Y+ Y+ VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC -REF Y- X- X- X- GND GND GND GND GND GND GND GND GND GND
Rev. 0 | Page 25 of 36
AD7879
15 PM1 PM0 GPIO EN GPIO DAT GPIO GPIO DIR POL SER/ DFR AVG1 AVG0 MED1 MED0 SW/ RST FCD3 FCD2 FCD1 FCD0 0
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Figure 30. Control Register 2
CONTROL REGISTER 2
Control Register 2 (Address 0x02) contains the power management bits, the GPIO settings, the SER/DFR bit (to choose single or differential methods of touch screen measurement), the averaging and median filter settings, a bit that allows resetting the part, and the first conversion delay bits. Its power-on default value is 0x4040. See the Detailed Register Descriptions section for more information on the control registers.
Power Management (Control Register 2, Bits[15:14])
The power management (PM) bits in Control Register 2 allow the power management features of the ADC to be programmed. If the PM bits are 00, the ADC is permanently powered down. This overrides any setting of the mode bits in Control Register 1. If the PM bits are 01, both the ADC and the reference power down when the ADC is not converting. If the PM bits are 10 or 11, the analog blocks to be powered down depend on the ADC mode settings. Power management overrides the ADC modes. Table 21. Power Management Selection
PM1 0 PM0 0 Function Full shutdown; ADC, oscillator, BIAS, and temperature sensor are all turned off. The only way of coming out of this mode is to write to the part over the serial interface and change the PM bits. This setting overrides any other setting on the part, including the ADC mode bits. The analog blocks to be powered down depend on the ADC mode settings. If the ADC mode is set to master mode, the ADC, BIAS, temperature sensor, and oscillator are powered down and must wake up when the user touches the screen. If the ADC mode is set to slave mode, the ADC and the TEMP sensor are powered down while not being used. They wake up automatically when required. The oscillator and BIAS are powered up because they are needed to measure time. This also applies to the single-conversion mode. ADC, BIAS, and the oscillator are powered up continuously irrespective of ADC mode. As 01.
First Conversion Delay (Control Register 2, Bits[3:0])
The first conversion delay (FCD) bits in Control Register 2 program a delay from 128 s (default) up to 4.096 ms before the first conversion to allow the ADC time to power up. This delay also occurs before conversion of the X and Y coordinate channels to allow extra time for screen settling, and after the last conversion in a sequence to precharge PENIRQ. Table 20. First Conversion Delay Selection
FCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Function 128 s 256 s 384 s 512 s 640 s 768 s 896 s 1.024 ms 1.152 ms 1.280 ms 1.536 ms 1.792 ms 2.048 ms 2.560 ms 3.584 ms 4.096 ms
0
1
1 1
0 1
Rev. 0 | Page 26 of 36
AD7879
15 AUX/ AUX/ AUX/ INT GPIO TEMP TEMP TEMP VBAT VBAT VBAT MODE ALERT LOW HIGH MASK LOW HIGH MASK X+ Y+ Z1 Z2 AUX 0 NOT VBAT TEMP USED
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Figure 31. Control Register 3
CONTROL REGISTER 3
Control Register 3 (Address 0x03) includes the interrupt register (Bits[15:8]) and Control Register 3 (Bits[7:0]).
01 IDLE ADC MODE? 10 SLAVE MODE
00
11 MASTER MODE
Sequencer
The sequencer bits control which channels are converted during a conversion sequence in both slave and master mode. To include a measurement in a sequence, the relevant bit must be set in the sequence. Setting Bit 7 includes a measurement on the X+ channel (Y position). Setting Bit 6 includes a measurement on the Y+ channel (X position), and so on. Figure 32 illustrates the correspondence between the bits in Control Register 3 and the various measurements. Bit 0 is not used.
SINGLE CONVERSION
CONVERSION SEQUENCE
WAIT FOR FIRST TOUCH
YES
CONVERSION SEQUENCE TIMER = 00? NO START TIMER SCREEN TOUCHED? YES WAIT FOR TIMER TIMER = 00? NO START TIMER YES NO
WAIT FOR TIMER
YES
Figure 32. Conversion Modes
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SCREEN TOUCHED?
NO
AD7879
START OF CONVERSION SEQUENCE SET CHANNEL
YES
FCD REQ'D? NO
START FCD TIMER
resets INT to a high condition. INT is also reset if a new conversion is started by the AD7879 because the timer expired. The host should read the results registers only when INT is low. To ensure correct operation of the DAV mode when using the SPI interface it is necessary to write 0x0000 to Register 0x81 after a set of register reads. This clears the internal data read signal.
INT
WAIT FOR FCD CONV_START = 1
AD7879
START ACQUIST TIMER AND WAIT FOR ACQUISITION
STATUS IDLE
SETUP BY HOST
ADC CONVERTING
NEW DATA HOST READS AVAILABLE RESULTS
IDLE
Figure 34. Operation of INT Output
CONV_START = 0
COMPARE NEW READING
CONVERT: WAIT FOR DATA_READY
When the on-board timer is programmed to perform automatic conversions, limited time is available to the host to read the results registers before another sequence of conversions begins. The INT signal is reset high when the timer expires, and the host should not access the results registers while INT is high.
SHIFT READINGS
YES
MAV FILTER ENABLED NO RUN AVERAGER NO FCD REQ'D
INT--Out of Limits
The INT pin operates as an alarm or interrupt output when Bit 13 in Register 0x03 is set to 1. The output goes low if any one of the interrupt sources is asserted. The results of high and low limit comparisons on the AUX, VBAT, and TEMP channels are interrupt sources. An out-of-limit comparison sets a status bit in the interrupt register. There are separate status bits for both the high and low limits on each channel to indicate which limit was exceeded. The interrupt sources can be masked by clearing the corresponding enable bit in this register. There is one enable bit per channel.
NO
MEDIAN WINDOW FINISHED? YES RUN FILTER AVERAGER
AVG FINISHED? YES
NO
LIMIT COMPARISON
TXFER DATA TO REG. MAP
OUT-OFLIMIT? NO
YES
PENIRQ-- Pen Interrupt
SET ALERT AND INTERRUPT NO EOCS ? NOTE THAT CONVERSION SEQUENCE MAY BE 1 CHANNEL ONLY (MODE 01). YES END OF CONVERSION SEQUENCE
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The pen interrupt request output (PENIRQ) goes low whenever the screen is touched and the PENIRQ enable bit is set to 0 (Control Register 1, Bit 15). When PENIRQ enable is set to 1, the pen interrupt request output is disabled. The pen interrupt equivalent output circuitry is outlined in Figure 35. This is a digital logic output with an internal 50 k pull-up resistor, which means it does not need an external pullup. The PENIRQ output idles high, and the PENIRQ circuitry is always enabled in master mode (ADC mode = 11), except during conversions.
Y+ VCC VCC 50k X+ X- TOUCH SCREEN PENIRQ ENABLE Y-
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Figure 33. Conversion Sequence
INTERRUPTS
The AD7879 has a dual function interrupt output, INT, as well as a pen down interrupt, PENIRQ. The INT output can be configured as a data available interrupt, as an out of limit interrupt, or as a GPIO interrupt.
INT--Data Available
The behavior of the interrupt output is controlled by Bit 13 in Control Register 3. In default mode, INT operates as a data available interrupt (Bit 13 = 0). When the AD7879 has finished a conversion or a conversion sequence, the interrupt asserts to let the host know that new ADC data is available in the result registers. While the ADC is idle or is converting, INT is high. When the ADC has finished converting and new data has been written to the results registers, INT goes low. Reading the result registers
Rev. 0 | Page 28 of 36
PENIRQ
Figure 35. PENIRQ Output Equivalent Circuit
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tCONV
AD7879
When the screen is touched, PENIRQ goes low. This generates an interrupt request to the host. When the screen touch ends, and if the ADC is idle, PENIRQ immediately goes high. If the ADC is converting, PENIRQ goes high when the ADC becomes idle. The PENIRQ operation for these two conditions is shown in Figure 36.
NOT SCREEN TOUCHED TOUCHED PENIRQ DETECTS TOUCH NOT TOUCHED
SYNCHRONIZING THE AD7879 TO THE HOST CPU
The two recommended methods for synchronizing the AD7879 to its host CPU are slave mode (in which the mode bits can be either 01b or 10b) and master mode (in which the mode bits are 11b). In master mode (ADC mode bits = 11b), PENIRQ mode can be used as an interrupt to the host. When PENIRQ goes low to indicate that the screen has been touched, the host is awakened. The host can then program the AD7879 to convert in any mode and read the results after the conversions are completed. In master mode, INT or DAV can also be used as an interrupt to the host. The host should first define a conversion sequence in Control Register 3, initialize the AD7879 in Mode 11b and enable INT or DAV using Bit 15 in Control Register 1 and Bit 13 in Control Register 3. The host can then enter sleep mode to conserve power. The wake-up on-touch feature of the AD7879 is active in this mode; therefore, when the screen is touched, the programmed sequence of conversions automatically begins. When the INT or DAVsignal asserts, the host reads the new data available in the AD7879 results registers and returns to sleep mode. This method can significantly reduce the load on the host. Figure 37 shows how the PENIRQ circuit is enabled. The wakeup on-touch circuit and the PENIRQ circuit are enabled only in master mode (ADC mode = 11). In slave mode, the PENIRQ/ DAV/INT pin can output only DAV or INT signals.
PENIRQ
PENIRQ DETECTS RELEASE ADC IDLE RELEASE NOT DETECTED
ADC STATUS
NOT SCREEN TOUCHED
TOUCHED PENIRQ DETECTS TOUCH
NOT TOUCHED
PENIRQ
ADC STATUS
ADC IDLE
ADC CONVERTING
ADC IDLE
Figure 36. PENIRQ Operation for ADC Idle and ADC Converting
YES
07667-036
PENIRQ DETECTS RELEASE
ADC MODE = 11? MASTER MODE
YES
ENABLE PENIRQ DETECTION CIRCUIT
TOUCH SCREEN TOUCHED
ENABLE WAKE UP ON TOUCH
TO THE DIGITAL CORE
DAV (END OF CONVERSION SEQUENCE) INT (GPIO ALERT/OUT OF LIMITS)
TOUCH SCREEN TOUCHED 0 INT/DAV/GPIO ALERT
0 PENIRQ/INT/DAV PIN 1 CONTROL REGISTER 1 BIT 15
1 CONTROL REGISTER 3 BIT 13
Figure 37. Master Mode Operation
Rev. 0 | Page 29 of 36
07667-037
AD7879 SERIAL INTERFACE
The AD7879 is available with an serial peripheral interface (SPI). The AD7879-1 is available with an I2C(R)-compatible interface. Both parts are the same, with the exception of the serial interface. It is recommended not to write to addresses outside the register map. Bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. Bits[9:0] contain the target register address. When reading or writing to more than one register, this address indicates the address of the first register to be written to or read from.
SPI INTERFACE
The AD7879 has a 4-wire SPI. The SPI has a data input pin (DIN) for inputting data to the device, a data output pin (DOUT) for reading data back from the device, and a data clock pin (SCL) for clocking data into and out of the device. A chip select pin (CS) enables or disables the serial interface. CS is required for correct operation of the SPI interface. Data is clocked out of the AD7879 on the negative edge of SCL and data is clocked into the device on the positive edge of SCL.
Writing Data
Data is written to the AD7879 in 16-bit words. The first word written to the device is the command word, with the read/write bit set to 0. The master then supplies the 16-bit input data-word on the DIN line. The AD7879 clocks the data into the register addressed in the command word. If there is more than one word of data to be clocked in, the AD7879 automatically increments the address pointer and clocks the next data-word into the following register. The AD7879 continues to clock in data on the SDA line until either the master finishes the write transition by pulling CS high, or until the address pointer reaches its maximum value. The AD7879 address pointer does not wrap around. When it reaches its maximum value, any data provided by the master on the DIN line is ignored by the AD7879.
SPI Command Word
All data transactions on the SPI bus begin with the master taking CS from high to low and sending out the command word. This indicates to the AD7879 whether the transaction is a read or a write, and gives the address of the register from which to begin the data transfer. The bit map in Table 22 shows the SPI command word. Table 22.
MSB 15 14 1 1 LSB 13 1 12 0 11 0 10 R/W 9:0 Register address
16-BIT COMMAND WORD ENABLE WORD DIN CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 D15 D14 D13 16-BIT DATA D2 D1 D0
t2
SCL 1 2 3 4 5
t4
6 7 8
t5
9 10 11 12 13 14 15 16 17 18 19 30 31 32
t1
CS
t3
t8
Figure 38. Single Register Write, SPI Timing
Rev. 0 | Page 30 of 36
07667-038
NOTES 1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
AD7879
16-BIT COMMAND WORD ENABLE WORD DIN
CW 15 CW 14 CW 13 CW 12 CW 11
R/W
CW 10 CW 9 CW 8
STARTING REGISTER ADDRESS
CW 7 CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 D15
DATA FOR STARTING REGISTER ADDRESS
D14 D1 D0 D15
DATA FOR NEXT REGISTER ADDRESS
D14 D1 D0 D15
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
CS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 39. Sequential Register Write SPI Timing
16-BIT COMMAND WORD ENABLE WORD DIN CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X
t2
SCL 1 2 3 4 5
t4
6 7 8
t5
9 10 11 12 13 14 15 16 17 18 19 30 31 32
t1
CS
t3
t8
t6
DOUT XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13 D2 D1
t7
D0 XXX
16-BIT READBACK DATA NOTES 1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN. 4. X DENOTES DON'T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 40. Single Register Read Back SPI Timing
Reading Data
A read transaction begins when the master writes the command word to the AD7879 with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7879 clocks out data from the addressed register on the SDA line. The first data-word is clocked out on the first falling edge of SCL following the command word, as shown in Figure 40.
The AD7879 continues to clock out data on the DOUT line provided the master continues to supply the clock signal on SCL. The read transaction finishes when the master takes CS high. If the AD7879 address pointer reaches its maximum value, the AD7879 repeatedly clocks out data from the addressed register. The address pointer does not wrap around.
Rev. 0 | Page 31 of 36
07667-040
07667-039
AD7879
16-BIT COMMAND WORD ENABLE WORD DIN CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X X X X
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
CS
DOUT
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
XXX XXX XXX
XXX XXX XXX
D15
D14
D1
D0
D15
D14
D1
D0
D15
READBACK DATA FOR STARTING REGISTER ADDRESS
READBACK DATA FOR NEXT REGISTER ADDRESS
Figure 41. Sequential Register Read Back SPI Timing
I2C-COMPATIBLE INTERFACE
The AD7879-1 supports the industry standard 2-wire I2C serial interface protocol. The two wires associated with the I2C timing are the SCL and SDA inputs. The SDA is an I/O pin that allows both register write and register read back operations. The AD7879-1 is always a slave device on the I2C serial interface bus. It has a 7-bit device address, Address 0101 1XX. The lower two bits are set by tying the ADD0 and ADD1 pins high or low. The AD7879-1 responds when the master device sends its device address over the bus. The AD7879-1 cannot initiate data transfers on the bus. Table 23. AD7879-1 I2C Device Address
ADD1 0 0 1 1 ADD0 0 1 0 1 I2C Address 0101 100 0101 101 0101 110 0101 111
All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices on the bus then remain idle while the selected device waits for data to be read from, or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in a sequence of nine clock pulses (eight bits of data followed by an acknowledge bit from the slave device). Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes are read or written, a stop condition is established. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If the AD7879 encounters a stop condition, it returns to its idle condition.
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that an address/data stream follows.
Rev. 0 | Page 32 of 36
07667-041
NOTES 1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDA: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDA PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON'T CARE. 6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
AD7879
START AD7879 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV DEV DEV A2 A1 A3 DEV A0 R/W ACK A7 A6 A1 A0 REGISTER ADDRESS[A7:A0]
t1
SCL 1 2 3 4 5 6
t3
7 8 9 10 11 16 17
t2
STOP REGISTER DATA[D15:D8] ACK D15 D14 D9 D8 ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK START
t8
AD7879 DEVICE ADDRESS DEV A6 DEV A5 DEV A4
t4
18 19 20 25 26 27 28
t5
29 34 35 36
t6
37
t7
1 2 3
NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE Xs ARE DON'T CARE BITS. 4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
Figure 42. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process of writing to the AD7879-1 over the I C bus is shown in Figure 42 and Figure 44. The device address is sent over the bus followed by the R/W bit set to 0. This is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. The address is contained in the 8 LSBs of the register address byte. The bit map in Table 24 shows the register address byte. Table 24.
MSB 7 Bit 7 LSB 6 Bit 6 5 4 3 2 Register Address Bit 5 Bit 4 Bit 3 Bit 2 1 Bit 1 0 Bit 0
2
All registers on the AD7879-1 have 16 bits. Two consecutive 8-bit data bytes are combined and written to the 16-bit registers. To avoid errors, all writes to the device must contain an even number of data bytes. To finish the transaction, the master generates a stop condition on SDA, or generates a repeat start condition if the master is to maintain control of the bus.
Reading Data Over the I2C Bus
To read from the AD7879-1, the address pointer register must first be set to the address of the required internal register. The master performs a write transaction and writes to the AD7879-1 to set the address pointer. The master then outputs a repeat start condition to keep control of the bus, or if this is not possible, the master ends the write transaction with a stop condition. A read transaction is initiated, with the R/W bit set to 1. The AD7879-1 supplies the upper eight bits of data from the addressed register in the first read back byte, followed by the lower eight bits in the next byte. This is shown in Figure 43 and Figure 44. Because the address pointer automatically increases after each read, the AD7879-1 continues to output readback data until the master puts a no acknowledge and a stop condition on the bus. If the address pointer reaches its maximum value, and the master continues to read from the part, the AD7879-1 repeatedly sends data from the last register addressed.
The third data byte contains the 8 MSBs of the data to be written to the internal register. The fourth data byte contains the 8 LSBs of data to be written to the internal register. The AD7879-1 address pointer register automatically increments after each write. This allows the master to sequentially write to all registers on the AD7879-1 in the same write transaction. However, the address pointer register does not wrap around after the last address. Any data written to the AD7879-1 after the address pointer has reached its maximum value is discarded.
Rev. 0 | Page 33 of 36
07667-042
AD7879
START AD7879-1 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV DEV DEV A2 A1 A3 DEV A0 R/W ACK A7 A6 A1 A0 ACK REGISTER ADDRESS[A7:A0]
t1
SCL 1 2 3 4 5 6
t3
7 8 9 10 11 16 17 18
t2
P SR DEV A6 AD7879-1 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK
t8
AD7879 DEVICE ADDRESS DEV A6 DEV A5 DEV A4
USING REPEATED START 19
t4
20 21 25 26 27 28 29
t5
30 35 36 37
t6
t7
1 2 3
P
S DEV A6
AD7879-1 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7
REGISTER DATA[D7:D0] D6 D1 D0 ACK
P
SEPARATE READ AND WRITE TRANSACTIONS 19
t4
20 21 25 26 27 28 29
t5
30 35 36 37
NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB Xs ARE DON'T CARE BITS. 5. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 6. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 43. Example of I2C Timing for Single Register Read Back Operation
WRITE
ACK
ACK
ACK
ACK
S
6-BIT DEVICE ADDRESS W
REGISTER ADDR [7:0]
WRITE DATA HIGH BYTE [15:8]
WRITE DATA LOW BYTE [7:0]
...
WRITE DATA HIGH BYTE [15:8]
WRITE DATA LOW BYTE [7:0]
ACK
P
READ (USING REPEATED START)
ACK
ACK SR
ACK
ACK
ACK
S
6-BIT DEVICE ADDRESS W
REGISTER ADDR [7:0]
6-BIT DEVICE R LOW BYTE
READ DATA ADDRESS
READ DATA HIGH BYTE [15:8]
...
READ DATA HIGH BYTE [15:8]
READ DATA LOW BYTE [7:0]
ACK
P
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
ACK
ACK
ACK
ACK
ACK
S
6-BIT DEVICE W ADDRESS
REGISTER ADDR [7:0]
P
S
6-BIT DEVICE R ADDRESS
READ DATA HIGH BYTE [15:8]
READ DATA LOW BYTE [7:0]
...
READ DATA HIGH BYTE [15:8]
READ DATA LOW BYTE [7:0]
ACK
P
07667-044
OUTPUT FROM MASTER OUTPUT FROM AD7879
S = START BIT P = STOP BIT SR = REPEATED START BIT R = READ BIT
W = WRITE BIT ACK = ACKNOWLEDGE BIT ACK = NO ACKNOWLEDGE BIT
Figure 44. Example of Sequential I2C Write and Read Back Operation
Rev. 0 | Page 34 of 36
07667-043
AD7879 GROUNDING AND LAYOUT
For detailed information on grounding and layout considerations for the AD7879, refer to the AN-577 Application Note, Layout and Grounding Recommendations for Touch Screen Digitizers. ance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the PCB. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. of copper to plug the via. Connect the PCB thermal pad to GND.
CHIP SCALE PACKAGES
The lands on the chip scale package (CP-16-10) are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. To avoid shorting, provide a clear-
WLCSP ASSEMBLY CONSIDERATIONS
For detailed information on the WLCSP PCB assembly and reliability, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package.
VOLTAGE REGULATOR 0.1F 0.1F TO 10F (OPTIONAL) MAIN BATTERY
16
15
14
13
VCC/REF
AUX/ VBAT/ GPIO
X+
CS
HOST
CS 12 11 10 9 INT SCLK MISO MOSI
1 2 3 4 TOUCH SCREEN
Y+ NC
PENIRQ/INT/DAV NC
AD7879
NC X- NC DOUT
GND
Y-
SCL
DIN
SPI INTERFACE
NC = NO CONNECT
5
6
7
8
Figure 45. Typical Application Circuit
Rev. 0 | Page 35 of 36
07667-045
AD7879 OUTLINE DIMENSIONS
1.67 1.61 1.55 0.65 0.59 0.53 SEATING PLANE 0.36 0.32 0.28 TOP VIEW
(BALL SIDE DOWN)
3
2
1 A
BALL 1 IDENTIFIER 2.07 2.01 1.95
B
0.50 BSC BALL PITCH
C
D
(BALL SIDE UP)
Figure 46. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-1) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX
13 16
0.60 MAX PIN 1 INDICATOR
1
PIN 1 INDICATOR
TOP VIEW
0.65 BSC 3.75 BSC SQ 0.50 0.40 0.30
12
EXPOSED PAD
(BOTTOM VIEW)
2.50 2.35 SQ 2.20
4
9 8 5
0.25 MIN 1.95 BSC
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4mm Very Thin Quad (CP-16-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7879ACBZ-RL 1 AD7879ACBZ-500R71 AD7879ACPZ-RL1 AD7879ACPZ-500R71 AD7879-1ACBZ-RL1 AD7879-1ACBZ-500R71 AD7879-1ACPZ-RL1 AD7879-1ACPZ-500R71 EVAL-AD7879EBZ1 EVAL-AD7879-1EBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Serial Interface Description SPI Interface SPI Interface SPI Interface SPI Interface I2C Interface I2C Interface I2C Interface I2C Interface SPI Interface I2C Interface
Package Description 12-Ball WLCSP 12-Ball WLCSP 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 12-Ball WLCSP 12-Ball WLCSP 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Evaluation Board
Package Option CB-12-1 CB-12-1 CP-16-10 CP-16-10 CB-12-1 CB-12-1 CP-16-10 CP-16-10
082008-A
SEATING PLANE
0.35 0.30 0.25
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
081607-A
0.28 0.24 0.20
0.17 0.15 0.13
BOTTOM VIEW
Branding T2Y T2Y
T0Q T0Q
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07667-0-10/08(0)
Rev. 0 | Page 36 of 36
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